The present invention relates to static information storage, and more particularly concerns an integrated-circuit semiconductor read/write memory whose storage cells additionally contain a personalizable, selectively readable pattern of read-only data.
Semiconductor memories are divided into two major categories. Read/write memories (sometimes mislabelled RAM) have storage cells whose contents are freely alterable, while read-only memories (termed ROM or ROS) contain fixed data which is not changeable except by a lengthy programming or personalization process.
Frequently, however, a need arises for a memory which is basically read/write, yet which can also evoke a fixed, non-volatile, latent-image data pattern. Microprocessor-based controllers and small data-processing systems, for example, commonly require initialization programs upon power-up, but these programs are thereafter dispensable and can be overwritten with operating programs or data. Several approaches have been taken to provide such a function. Physically separate read/write and read-only memory integrated-circuit chips may be selectively enabled in the same address space, for instance. Separate read/write and read-only storage cells may be placed on the same chip, as in U.S. Pat. No. 4,193,128 to Brewer. Separate transistors may even be placed in the same cell to provide these two modes, as in U.S. Pat. No. 4,095,281 to Denes. Geometric asymmetry of a read/write cell for storing read-only data has been proposed in U.S. Pat. Nos. 3,662,351 and 3,820,086 to Ho et al, in U.S. Pat. No. 3,801,967 to Berger et al and in the IBM Technical Disclosure Bulletin, May 1975, pages 3634-35 by Balasubramanian et al. The use of asymmetry, however, requires a balanced multi-transistor storage cell of large size, as does the Denes system. Dennison et al have suggested, IBM Technical Disclosure Bulletin, June 1978, pages 190-93 and id., October 1978, pages 1902-03, the replacement of these large static cells with single-transistor dynamic storage cells having capacitive storage elements whose leakage can be varied to attain a read-only mode of operation. Such a memory chip requires bulky peripheral sources of light or other energy for operation, and its fabrication would be difficult and expensive.